Known from U.S. Pat. Nos. 5,218,569 and 5,394,362 are multi-level non-volatile memories of this type. The construction of a FLASH EEPROM multi-level memory is also described in an article TA 7.7, "A Multilevel Cell 32 Mb Flash Memory", ISSCC95 Conference, Feb. 16, 1995.
These publications also tackle the reading problem, that is the difficulty of discriminating among four different, fairly tightly packed levels for the cell threshold voltages.
From U.S. Pat. No. 4,964,079 a particular read circuit for multi-level non-volatile memories of this type is known.
All these read circuits and methods provide for the application, between the gate and source terminals of a cell being read, of a read voltage from a row decoding circuit which is powered by a supply circuit. The current flowing into the channel of the MOS transistor, or the voltage at the drain terminal, for example, is then measured and compared to currents or voltages having reference values.
This is also the case with two-level memories. Known from U.S. Pat. No. 5,291,446 is a power supply circuit for a row decoding circuit which suits the effectuation of read, write, and erase operations on two-level non-volatile memories. This power supply circuit comprises a read voltage generating section effective on request to output a voltage corresponding to the supply voltage, a write voltage generating section effective on request to output a boosted positive voltage with respect to the supply voltage, and an erase voltage generating section effective on request to output a highly negative voltage with respect to ground.
The present invention sets out from the idea of having the different threshold voltage levels for multi-level non-volatile memories sufficiently spaced apart to make the read circuit significantly less critical.
The situation is complicated, however, by the distribution of the various cell characteristics after write and/or erase operations, accurate as these may be.